This invention relates generally to electronic design of digital integrated circuits, and more particularly to device-based random variability modeling in timing analysis of digital integrated circuits, and/or modeling of other timing impact factors that can influence the timing analysis.
As technology dimensions continue to shrink, device variability continues to increase. In addition, the inherent performance advantages of new technology generations are eroding. Traditionally, variability has been accounted for in integrated circuit design by margining during analysis. In order to ensure functionality, the margin values are calculated based on ‘worst case’ device characteristics and application conditions. With decreasing performance advantage and increasing variability, the use of broad, bounding margins is no longer viable.
There are known techniques for a more refined handling of variability in the industry. Most of these techniques focus on gate-specific variability analysis for gate-level designs. A few methods apply to device-level custom design, but require simulation and/or Monte Carlo analysis, which is impractical for application during timing analysis.
Device-level custom design is typically critical for closure of very high speed, complex functions in advanced technologies. Gate-level design is typically critical for efficient closure of lower speed, less complex functions. Traditionally, device-level custom designs and gate-level designs were contained on separate chips. Denser technologies allow more functions to be combined on a single chip, driving the integration of gate-level and device-level custom designs.